Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023

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6.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst)

The synchronous reset synchronizer parameterizable macro (ipm_cdc_sync_rst) synchronizes a synchronous reset signal to the destination clock domain. The generated output both asserts and de-asserts synchronously to the destination clock domain. The number of the synchronizer stages is configurable, allowing a range from three to ten stages. The default reset type is ACTIVE_HIGH, but you can specify the ACTIVE_HIGH or ACTIVE_LOW type of the reset signal with the RST_TYPE parameter.

Figure 7. Synchronous Reset Synchronizer Parameterizable Macro Block Diagram