Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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6.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions

Table 13.  Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions
Port Type Width Required Description
clk Input 1 Yes Synchronizer reset clock port.
arst_in Input 1 Yes Asynchronous reset input port.
srst_out Output 1 Yes Synchronous reset output port.