Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023

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5.1. I/O PLL Parameterizable Macro Port Descriptions

Table 9.  I/O PLL Parameterizable Macro Port Descriptions
Port Type Required Description
reflck Input Required The reference clock that drives the I/O PLL.
reset Input Required The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
outclk[] Output Optional Output Clock from the I/O PLL.
locked Output Optional This port is driven high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.