Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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6.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions

Table 15.  Synchronizer Using Single Clock Parameterizable Macro Port Descriptions
Port Type Width Required Description
clk Input 1 Yes Synchronizer clock.
async_in Input 1 Yes Input signal asynchronous to clk.
sync_out Output 1 Yes Output signal synchronized to output clock domain.