Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023

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5.2. I/O PLL Parameterizable Macro Parameters

Table 10.  I/O PLL Parameterizable Macro Parameters
Parameter Allowed Values Description
REFERENCE_CLOCK_FREQUENCY 10.0 MHz 1100.0 MHz Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum values are dependent on the target device.
N_CNT 1-110 Specifies the divide factor of N-counter.
M_CNT 4-160 Specifies the multiply factor of M-counter.
C[ ]_CNT 1-510 Specifies the divide factor for the output clock (C-counter). The number of C-counter supported is seven.
PLL_SIM_MODEL " " It is a simulation specific parameter to select the technology dependent I/O PLL simulation model. Allowed values are "Stratix 10", "Agilex 7 F-Series", "Agilex 7 (F-Series)", "Agilex 7 I-Series", "Agilex 7 (I-Series)", "Agilex 7 M-Series", "Agilex 7 (M-series)"