Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 10/02/2023
Public

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6.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template

Synchronizer Using Two Clocks SystemVerilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//IPM_CDC_2CLKS_SYNC
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_2clks_sync.sv
	
   ipm_cdc_2clks_sync #(
      .INITIAL_VALUE                  (0),
      .NUM_STAGES                     (3)
	) <instance_name> (
      .src_clk     (_connected_to_src_clk_),  //input, width = 1
      .src_sig     (_connected_to_src_sig_),  //input, width = 1
      .dst_clk     (_connected_to_dst_clk_),  //input, width = 1
      .dst_sig     (_connected_to_dst_sig_)   //output, width = 1
	);