F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
Public

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7.3. Transceivers

The transceiver provides physical lane with the line rate of 25.78125 Gbps.
Table 12.  Transceiver Signals

Signal

Direction

Description

O_tx_serial Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
i_rx_serial Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.