F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
Public

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5.1.3.2. IP Core Malformed Packet Handling

While receiving an incoming packet from the Ethernet link, the F-Tile Low Latency 50G Ethernet Intel® FPGA IP expects to detect a terminate character at the end of the packet. When it detects an expected terminate character, the IP core generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control character when it expects a terminate character.

If the IP core detects an Error character, a Start character, an IDLE character, or any other non-terminate control character, when it expects a terminate character, it performs the following actions:

  • Generates an EOP.
  • Asserts a malformed packet error (l1_rx_error[0]).
  • Asserts an FCS error (l1_rx_error[1]).

If the IP core subsequently detects a terminate character, it does not generate another EOP indication.

When the IP core receives a packet that contains an error deliberately introduced on the Ethernet link using the F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX error insertion feature, the IP core identifies it as a malformed packet.

At this time, the F-Tile Low Latency 50G Ethernet Intel® FPGA IP does not recognize non-zero 4-bit ordered set types as an error.