F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
ID
758946
Date
10/02/2023
Public
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Ixiasoft
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
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Ixiasoft
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
Updated for: |
---|
Intel® Quartus® Prime Design Suite 23.3 |
IP Version 3.0.0 |
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Low Latency 50G Ethernet Intel® FPGA IP for the Intel Agilex® 7 (F-Tile) devices.
Intended Audience
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
Related Documents
The following table lists other reference documents which are related to the protocol.
Reference | Description |
---|---|
F-Tile Low Latency 50G Ethernet Intel® FPGA IP Release Notes | Lists the changes made for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP in a particular release. |
Low Latency 50G Ethernet Intel FPGA IP Intel® FPGA IP Release Notes | Lists the changes made for the 50G Ethernet Intel FPGA IP in a particular release. |
Acronyms and Glossary
Acronym | Expansion |
---|---|
ALM | Adaptive Logic Element |
AVMM | Avalon® memory-mapped interface |
AVST | Avalon® streaming interface |
AXI | ARM corporation's Advanced Extensible Interface |
CRC | Cyclic redundancy code |
CSR | Control and Status Register |
EMIB | Intel Embedded Silicon Bridge technology |
FCQN | Flow Control Queue Number |
FPGA | Field Programmable Gate Array |
LAB | Logic Array Block |
MAC | Media Access Control |
MLAB | Memory Logic Array Block |
PCS | Physical coding sublayer |
PFC | Priority-based flow control |
PHY | Physical layer |
PLL | Phase-locked loop |
PMA | Physical medium attachment |
QN | Queue Number |