F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
Public

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5.1.2. 50 GbE TX PCS

The TX PCS datapath consists of:
  • TX PCS encoder—encodes the data from the PMA interface.
  • TX PCS scrambler—enables the data to be scrambled. Channels do not lock correctly if the data is not scrambled.
  • Striper—enables logically sequential data to be segmented to increase data throughput.