F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
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7.7. Flow Control Signals

Table 17.  Flow Control Interface
Signal Name Direction Width Description
pause_insert_tx0 Input QN

These signals are available only if Pause or PFC flow control support is synthesized. These indicates the MAC if a XON or XOFF Pause or PFC flow control frame should be sent.

FCQN = 1 for Pause

FCQN = 1 to 8 for PFC

The request for XON/XOFF flow control frame transmission can be done in either 1 or 2-bit request mode (see pause_insert_tx1).

1-bit mode request model:

  • 0 = No request
  • 0 to 1 = Generate XOFF request
  • 1 = Continue generate XOFF request
  • 1 to 0 = Generate XON request

2-bit mode request model:

Represents the lower bit. Only takes effect when the CSR of 2-bit Flow Control Request mode selects “Signal”.

  • 00 = No request
  • 01 = XON request
  • 10 = XOFF request
  • 11 = Invalid
pause_insert_tx1 Input QN

Use in conjunction with pause_insert_tx0 to form a 2-bit request for XON/XOFF flow control frame transmission. This represents the upper bit of the 2-bit control.

pause_receive_rx Output   Asserted to indicate an RX pause signal match. The IP core asserts bit [n] of this signal when it receives a pause request with an address match, to signal the TX MAC to throttle its transmissions from priority queue [n] on the Ethernet link.