F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
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3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP

The transceivers require a separately instantiated F-Tile Reference and System PLL Clocks to generate the transceiver and system PLL reference clock.

In your IP design, you must include an F-Tile Reference and System PLL Clocks Intel® FPGA IP core to pass logic generation flow. The F-Tile Reference and System PLL Clocks Intel FPGA IP must always connect to a protocol based Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel® FPGA IP cannot be compiled or simulated as a standalone IP. For more information on parameters and port list for F-Tile Reference and System PLL Clocks Intel® FPGA IP core, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

The SYS PLL configuration for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP:
  • Mode of System PLL: ETHERNET_FREQ_805_156, ETHERNET_FREQ_805_312, ETHERNET_FREQ_805_322
  • FGT Refclk frequency: 156.25 MHz/312.50 MHz/322.27 MHz
Figure 6. PLL Configuration Example for F-Tile Low Latency 50G Ethernet Intel® FPGA IP Configuration

For more information, refer to the F-Tile Ethernet Intel FPGA IP Hard IP User Guide.