F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
Public

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5.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Functional Description

The F-Tile Low Latency 50G Ethernet Intel® FPGA IP implements an Ethernet MAC in accordance with the 25G & 50G Ethernet Specification. The IP core implements an Ethernet PCS and PMA (PHY) that handles the frame encapsulation and flow of data between a client logic and Ethernet network.

Figure 7.  F-Tile Low Latency 50G Ethernet Intel® FPGA IP with MAC, PCS, and PMA Clock Diagram

In the TX direction, the MAC assembles packets and sends them to the PHY. It completes the following tasks:

  • Accepts client frames.
  • Inserts the inter-packet gap (IPG), preamble, start of frame delimiter (SFD), and padding. The source of the preamble and SFD depends on whether the IP core is in preamble-pass-through mode.
  • Adds the CRC bits if enabled.
  • Updates statistics counters if enabled.

The PCS encodes MAC frames. The PHY performs reliable transmission over the media to the remote end. The PCS and PMA blocks are implemented based on the F-Tile Ethernet Hard IP.

In the RX direction, the PMA, if selected, passes frames to the PCS that sends them to the MAC. The MAC completes the following tasks:

  • Performs CRC and malformed packet checks.
  • Updates statistics counters if enabled.
  • Strips out the CRC, preamble, and SFD.
  • Passes the remainder of the frame to the client.

In preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. In RX CRC pass-through mode, the MAC passes on the CRC bytes to the client and asserts the end-of-packet signal in the same clock cycle as the final CRC byte.