F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 10/02/2023
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7.2. RX MAC Interface to User Logic

The user interface for the MAC receive direction is a Avalon® streaming interface. A valid FCS for a packet results in l1_rx_error bit 1 being low when l1_rx_endofpacket is high. An FCS violation is indicated when l1_rx_error bit 1 is high when l1_rx_endofpacket is high.
Table 11.   Avalon® Streaming RX Datapath All interface signals are clocked by the clk_rxmac clock.

Signal

Direction

Description

clk_rxmac Output rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz. All RX MAC interface signals are synchronous to clk_rxmac .
l1_rx_data[127:0] Output

Data output from the MAC. Bit[127] is the MSB and bit[0] is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when nullnull

l1_rx_valid Output When asserted, indicates that l1_rx_data[63:0] is driving valid data. When this signal is low,l1_rx_data, l1_rx_startofpocket, l1_rx_endofpacket, l1_rx_empty, and l1_rx_error are ignored.
l1_rx_startofpacket Output

When asserted, indicates the first byte of a frame.

l1_rx_endofpacket Output When asserted, indicates the last data byte of a frame before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l1_rx_empty[2:0] Output Specifies the number of empty bytes when l1_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.

l1_rx_error[5:0] Output

When asserted in the same cycle as l1_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l1_rx_error specify the following errors:

  • l1_rx_error[5]: Unused.
  • l1_rx_error[4]: Payload length error. If the length field is <1535 bytes (0x600 bytes), the received payload length is less than what is advertised in the payload length field.
  • l1_rx_error[3]: Oversized frame. The frame size is greater than the value specified in the MAX_RX_SIZE_CONFIG register.
  • l1_rx_error[2]: Undersized frame – The frame size is less than 64 bytes. Frame size = header size + payload size.
  • l1_rx_error[1]: CRC Error. The computed CRC value differs from the received CRC.
  • l1_rx_error[0]: Malformed packet. The packet is terminated with a non-terminate control character. When this bit is asserted, l1_rx_error[1] is also asserted.
l1_rxstatus_valid Output When asserted, indicates that l1_rxstatus_data is driving valid data.
l1_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
pause_receive_rx[FCQN-1:0] Output This signal is available if you turn on Enable flow control in the parameter editor. Each bit of pause_receive_rx[FCQN-1:0] indicates that the corresponding queue is being paused.
Figure 20.  50G Ethernet Intel FPGA IP MAC to Client Avalon® Streaming Interface l1_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l1_rx_data[63:56] , 0xfbe4 . . . in this timing diagram.