AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

ID 750856
Date 11/14/2022

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Updating the Top-Level Design

To update the file with the PR_IP instance:

  1. To add the external_host_pr_ip instance to the top-level design, uncomment the following code blocks in the file:
    // Status signals from external PR IP
    input wire pr_request,
    output_wire pr_done,
    output_wire [1:0] pr_error
    wire    clock_out;
    external_host_pr_ip u_pr_ip
    .outclk        (clock_out),
    .reset         (1'b0),
    .pr_request    (pr_request),
    .pr_done       (pr_done),
    .pr_error      (pr_error)
  2. Save the file.