AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

ID 750856
Date 11/14/2022

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Step 6: Creating Revisions

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.

From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

To compile a PR design, you must create a PR implementation revision for each persona. In addition, you must assign revision types for each of the revisions. The available revision types are:

  • Partial Reconfiguration - Base
  • Partial Reconfiguration - Persona Implementation

The following table lists the revision name and the revision type for each of the revisions:

Table 4.  Revision Names and Types
Revision Name Revision Type
blinking_led.qsf Partial Reconfiguration - Base
blinking_led_default.qsf Partial Reconfiguration - Persona Implementation
blinking_led_slow.qsf Partial Reconfiguration - Persona Implementation
blinking_led_empty.qsf Partial Reconfiguration - Persona Implementation