AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board
ID
750856
Date
11/14/2022
Public
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Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Reference Design Requirements
Use of this reference design requires the following:
- Installation of the Intel® Quartus® Prime Pro Edition version 22.3 with support for the Intel® Agilex® device family.
- Connection to the Intel® Agilex® F-Series FPGA development board on the bench.
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Download of the design example available in the following location:
https://github.com/intel/fpga-partial-reconfig
To download the design example:
- Click Clone or download.
- Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/agilex_external_pr_configuration subfolder to access the reference design.