AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design
Reference Design Overview
The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design that do not impact operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the Intel® Quartus® Prime Pro Edition software introduces a new and simplified compilation flow for partial reconfiguration.
This Intel® Agilex® reference design uses the Partial Reconfiguration External Configuration Controller Intel FPGA IP and has a simple PR region.
External Host Configuration
In external host configuration, you must first create a host design in an external device to host the PR process, as Intel Agilex Device External Host Hardware Setup shows. The host design streams configuration data to the Intel® Agilex® Avalon streaming interface pins that correspond to the PR handshaking signals that come from the Partial Reconfiguration External Configuration Controller Intel FPGA IP. The PR pins that you use to connect both devices can be any available user I/Os.
The following sequence describes the partial reconfiguration via configuration pins operation:
- First assert the pr_request pin that is connected to the Partial Reconfiguration External Configuration Controller Intel FPGA IP.
- The IP asserts a busy signal to indicate that the PR process is in progress (optional).
- If the configuration system is ready to undergo a PR operation, the avst_ready pin is asserted indicating that it is ready to accept data.
- Begin to stream the PR configuration data over the avst_data pins and the avst_valid pin, while observing the Avalon streaming specification for data transfer with backpressure.
- Streaming stops whenever the avst_ready pin is de-asserted.
- After streaming all configuration data, the avst_ready pin is de-asserted to indicate that no more data is required for PR operation.
- The Partial Reconfiguration External Configuration Controller Intel FPGA IP de-asserts the busy signal to indicate the end of the process (optional).
- You can check the pr_done and pr_error pins to confirm whether the PR operation completed successfully. If an error occurs, such as failure in version checking and authorization checking, the PR operation terminates.
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