AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board
ID
750856
Date
11/14/2022
Public
A newer version of this document is available. Customers should click here to go to the newest version.
Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Step 1: Getting Started
To copy the reference design files to your working environment and compile the blinking_led flat design:
- Create a directory in your working environment, agilex_pcie_devkit_blinking_led_pr.
- Copy the downloaded tutorials/agilex_pcie_devkit_blinking_led/flat sub-folder to the directory, agilex_pcie_devkit_blinking_led_pr.
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
- To elaborate the hierarchy of the flat design, click Processing > Start > Start Analysis & Synthesis. Alternatively, at the command-line, run the following command:
quartus_syn blinking_led -c blinking_led