AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board
ID
750856
Date
11/14/2022
Public
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Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
1. Answers to Top FAQs
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| Intel® Quartus® Prime Design Suite 22.3 |
| What is PR via configuration pins? |
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| What do I need for this reference design? |
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| Where can I get the reference design? |
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| How do I perform PR via external configuration? |
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| What is a PR persona? |
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| How do I program the board? |
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| What are the PR known issues and limitations? |
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| Do you have training on PR? |