AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

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ID 750856
Date 11/14/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
1. Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design

Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2022.11.14 22.3
  • Initial release.
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