AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board
ID
750856
Date
11/14/2022
Public
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Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Step 7: Compiling the Base Revision
- To compile the base revision, click Processing > Start Compilation. Alternatively, the following command compiles the base revision:
quartus_sh --flow compile blinking_led -c blinking_led - Inspect the bitstream files that generate in the output_files directory.
Table 5. Generated Files Name Type Description blinking_led.sof Base programming file Used for full-chip base configuration blinking_led.pr_partition.rbf PR bitstream file for base persona Used for partial reconfiguration of base persona. blinking_led_static.qdb .qdb database file Finalized database file used to import the static region.