External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Overview, Design Flow, and General Information

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ID 710283
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents
1. Introduction to Intel® Memory Solutions 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to Intel® Memory Solutions
1.1. Memory Solutions 1.2. Protocol Support Matrix 1.3. Arria 10 EMIF Future Protocol Support 1.4. Document Revision History
2. Recommended Design Flow
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. LPDDR3 Features 3.8. Memory Selection 3.9. Example of High-Speed Memory in Embedded Processor 3.10. Example of High-Speed Memory in Telecom 3.11. Document Revision History
4. Selecting Your FPGA Device
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to Intel® Memory Solutions
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

1. Introduction to Intel® Memory Solutions

Updated for:
Intel® Quartus® Prime Design Suite 17.0
The following topics provide an overview of Intel® 's External Memory Interface solutions.

Intel provides the fastest, most efficient, and lowest latency memory interface IP cores. Intel® 's external memory interface IP is designed to easily interface with today's higher speed memory devices.

Intel® supports a wide variety of memory interfaces suitable for applications ranging from routers and switches to video cameras. You can easily implement Intel® ’s intellectual property (IP) using the memory IP core functions through the Quartus® Prime software. The Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA device.

Refer to the External Memory Interface Spec Estimator page for the maximum speeds supported by Intel® FPGAs.


Section Content
Memory Solutions
Protocol Support Matrix
Arria 10 EMIF Future Protocol Support
Document Revision History

Related Information
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