External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

3.7. Memory Selection

One of the first considerations in choosing a high-speed memory is data bandwidth. Based on the system requirements, an approximate data rate to the external memory should be determined. You must also consider other memory attributes, including how much memory is required (density), how much latency can be tolerated, what is the power budget, and whether the system is cost sensitive.

The following table lists memory features and target markets of each technology.

Table 3.  Memory Selection Overview

Parameter

LPDDR2

DDR3 SDRAM

DDR2 SDRAM

DDR SDRAM

RLDRAM II

RLDRAM 3

QDR II/+ SRAM

Bandwidth for 32 bit interface  (1)

25.6

59.7

25.6

12.8

25.6

35.8

44.8

Bandwidth at % Efficiency (Gbps)  (2)

17.9

41.7

17.9

9

17.9

–

38.1

Performance / Clock frequency

167–400 MHz (3)

300–933 MHz

167–400 MHz (3)

100–200 MHz

200–533 MHz

200–800 MHz

154–350 MHz

Intel® -supported data rate

Up to 1,066 Mbps

Up to 2,133 Mbps

Up to 1,066 Mbps

Up to 400 Mbps

Up to 1066 Mbps

Up to 1600 Mbps

Up to 1400 Mbps

Density

64 MB –8 GB

512 MB–8 GB,32 MB –8 GB (DIMM)

256 MB–1 GB,32 MB –4 GB (DIMM)

128 MB–1 GB, 32 MB –2 GB (DIMM)

288 MB,576 MB

576 MB – 1.1 GB

18–144 MB

I/O standard

HSUL- 12 1.2V

SSTL-15 Class I, II

SSTL-18 Class I, II

SSTL-2 Class I, II

HSTL-1.8V/1.5V

HSTL-1.2V and SSTL-12

HSTL-1.8V/1.5V

Data group width

8, 16, 32

4, 8, 16

4, 8, 16

4, 8, 16, 32

9, 18, 36

18, 36

9, 18, 36

Burst length

4, 8, 16

8

4, 8

2, 4, 8

2, 4, 8

2, 4, 8

2, 4

Number of banks

4, 8

8

8 (>1 GB), 4

4

8

16

—

Row/column access

Row before column

Row before column

Row before column

Row before column

Row and column together or multiplexed option

Row and column together or multiplexed option

—

CAS latency (CL)

—

5, 6, 7, 8, 9, 10

3, 4, 5

2, 2.5, 3

—

—

—

Posted CAS additive latency (AL)

—

0, CL-1, CL-2

0, 1, 2, 3, 4

—

—

—

—

Read latency (RL)

3, 4, 5, 6, 7, 8

RL = CL + AL

RL = CL + AL

RL = CL

3, 4, 5, 6, 7, 8

3-16

1.5, 2, and 2.5 clock cycles

On-die termination

—

Yes

Yes

No

Yes

Yes

Yes

Data strobe

Differential bidirectional

Differential bidirectional strobe only

Differential or single-ended bidirectional strobe

Single-ended bidirectional strobe

Free-running differential read and write clocks

Free-running differential read and write clocks

Free-running read and write clocks

Refresh requirement

Yes

Yes

Yes

Yes

Yes

Yes

No

Relative cost comparison

Higher than DDR SDRAM

Presently lower than DDR2

Less than DDR SDRAM with market acceptance

Low

Higher than DDR SDRAM,less than SRAM

Higher than DDR SDRAM,less than SRAM

Highest

Target market

Mobile devices that target low operating power

Desktops, servers, storage, LCDs, displays, networking, and communication equipment

Desktops, servers, storage, LCDs, displays, networking, and communication equipment

Desktops, servers, storage, LCDs, displays, networking, and communication equipment

Main memory, cache memory, networking, packet processing, and traffic management

Main memory, cache memory, networking, packet processing, and traffic management

Cache memory, routers, ATM switches, packet memories, lookup, and classification memories

Notes to Table:

  1. 32-bit data bus operating at the maximum supported frequency in a Stratix® V FPGA.
  2. 70% efficiency for DDR memories, which takes into consideration the bus turnaround, refresh, infinite burst length and random access latency and assumes 85% efficiency for QDR memories.
  3. The lower frequency limit depends on the higher of the DLL frequency and the minimum operating frequency of the given EMIF protocol. (Except for DDR2 interfaces running on Stratix V devices.)

Intel® supports the memory interfaces, provides various IP for the physical interface and the controller, and offers many reference designs; refer to Intel® ’s Memory Solutions Center.

For performance characteristics of the various high-speed memory interfaces, refer to the External Memory Interface Spec Estimator page on the Intel® website.

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