External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families
ID
710283
Date
3/06/2023
Public
2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
4.6. Device Settings Selection
After you have selected the appropriate FPGA device family for your memory interface, configure the device settings of your selected FPGA device family to meet your design needs.
Refer to the device ordering code and determine the appropriate device settings for your target device family.
For more information about the ordering code for your target device, refer to the “Ordering Information” section in volume 1 of the respective device handbooks.
The following sections describe the ordering code and how to select the appropriate device settings based on the ordering code to meet the requirements of your external memory interface.