External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts Device Density I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

4.6.4. Device Density and I/O Pin Counts

An FPGA device of the same device family and package size also varies in terms of device density and I/O pin counts.

For example, after you have selected the Stratix IV device family with the F780 packaging option, you must determine the type of device models that ranges from EP4GX70 to EP4GX230. Each of these devices has similar speed grades that range from grade 2 to grade 4, but are different in density.

Device Density

Device density refers to the number of logic elements (LEs). For example, PLLs, memory blocks, and so on. An FPGA device with higher density contains more logic elements in less area.

I/O Pin Counts

To meet the growing demand for memory bandwidth and memory data rates, memory interface systems use parallel memory channels and multiple controller interfaces. However, the number of memory channels is limited by the package pin count of the Intel® devices. Therefore, you must consider device pin count when you select a device; you must select a device with enough I/O pins for your memory interface requirement.

The number of device pins required depends on the memory standard, the number of memory interfaces, and the memory data width. For example, a ×72 DDR3 SDRAM single‑rank interface requires 125 I/O pins:

  • 72 DQ pins (including ECC)
  • 9 DM pins
  • 9 DQS, DQSn differential pin pairs
  • 17 address pins (address and bank address)
  • 7 command pins (CAS, RAS, WE, CKE, ODT, reset, and CS)
  • 1 CK, CK# differential pin pair
Note: For more information about the number of embedded memory, PLLs and user I/O counts that are available for your device, refer to the respective device handbooks. For the number of DQS groups available for each FPGA device, refer to the respective device handbooks.
Note: For the maximum number of controllers that is supported by the FPGAs for different memory types, refer to the Planning Pin and FPGA Resources chapter.

Intel® devices do not limit the interface widths beyond the following requirements:

  • The DQS, DQ, clock, and address signals of the entire interface must reside within the same bank or side of the device if possible, to achieve better performance. Although wraparound interfaces are also supported at limited frequencies.
  • The maximum possible interface width in any particular device is limited by the number of DQS and DQ groups available within that bank or side.
  • Sufficient regional clock networks are available to the interface PLL to allow implementation within the required number of quadrants.
  • Sufficient spare pins exist within the chosen bank or side of the device to include all other clock, address, and command pin placement requirements.
  • The greater the number of banks, the greater the skew. Intel® recommends that you always compile a test project of your desired configuration and confirm that it meets timing requirement.

Your pin count calculation also determines which device side to use (top or bottom, left or right, and wraparound).

Note: When assigning DQS and DQ pins in Arria® II GX devices, you are allowed to use only twelve of the sixteen I/O pins in an I/O module as DQ pins. The remaining four pins can be used only as input pins.
Note: For DQS groups pin-out restriction format, refer to Arria II GX Pin Connection Guidelines.
Note: The Arria II GX and Stratix V devices do not support interfaces on the left side of the device. There are no user I/O pins, other than the transceiver pins available in these devices.
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