External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

1.3. Document Revision History

Date Version Changes
March 2023 2023.03.06
  • Added subtitle to volume title.
  • Replaced Introduction to Memory Solutions topic with Introduction to this Handbook topic.
  • Added note and links to Introduction to this Handbook topic.
  • Removed Intel® Arria® 10 and Intel® Stratix® 10 references from the Protocol Support Matrix topic.
  • Removed Arria 10 EMIF Future Protocol Support topic.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Added Stratix 10 support statement to notes at the bottom of the Protocol Support Matrix.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02 Maintenance release.
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
  • Changed Arria 10 EMIF current support for LPDDR3 to yes.
  • Added LPDDR3 to product support matrix.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Added QDR IV and MAX 10 support to the Protocol Support Matrix.
August 2014 2014.08.15
  • Added information for Quartus II software versions 14.0 and 14.0 Arria 10 Edition to Altera Memory Types, PHY, and Controllers in the Quartus II Software table.
  • Added QDR II, QDR II+, and QDR II+ Xtreme support for Arria 10 to the Protocol Support Matrix.
  • Updated DDR3, DDR4, QDR II+ / QDR II+ Extreme, and RLDRAM 3 support in the Arria 10 EMIF Future Protocol Support table.
December 2013 2013.12.16
  • Added Arria 10 and DDR4 information to Protocol Support Matrix and Memory Solutions.
  • Combined Soft and Hard Memory IP and Memory Solutions sections.
  • Removed HardCopy III/IV from Protocol Support Matrix.
  • Added note to Protocol Support Matrix that RTL-based sequencer is not available for QDR II or RLDRAM II interfaces targeting Arria V devices
November 2012 2.0
  • Added Arria V GZ information.
  • Added RLDRAM III information to Protocol Support Matrix and Memory Solutions.
June 2012 1.2 Change to Table 1–3.
June 2012 1.1
  • Added Protocol Support Matrix.
  • Added Feedback icon.
November 2011 1.0 Initial release.
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