External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

ID 710283
Date 3/06/2023
Public
Document Table of Contents

2.1.7. Performing Functional Simulation

Simulate your design to determine correct operation, timing closure, and overall latency.
  1. Simulate your design using the RTL functional model.
  2. Use the IP functional simulation model with your own driver logic, testbench, and a memory model, to ensure correct read and write transactions to the memory.
  3. You may need to prepare the memory functional model by setting the speed grade and device bus mode.