Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 12/21/2022
Document Table of Contents

5.1. Quick Start Example (Active-HDL VHDL)

You can adapt the following RTL simulation example to get started quickly with Active-HDL:
  1. To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
    set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <Active HDL executable path>
    set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (VHDL)"
  2. Compile simulation model libraries using one of the following methods:
    • To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
    • Compile Intel FPGA simulation models manually:
      vlib <library1> <altera_library1> 
      vcom -strict93 -dbg -work <library1> <lib1_component/pack.vhd> \

    Use the compiled simulation model libraries during simulation of your design. Refer to your EDA simulator's documentation for information about running simulation.

  3. Open the Active-HDL simulator.
  4. Create and open the workspace:
    createdesign <workspace name> <workspace path>
    opendesign -a <workspace name>.adf
  5. Create the work library and compile the netlist and testbench files:
    vlib work
    vcom  -strict93  -dbg -work work <output netlist> <testbench file> 
  6. Load the design:
    vsim +access+r -t 1ps +transport_int_delays +transport_path_delays \
    -L work -L <lib1> -L <lib2> work.<testbench module name> 
  7. Run the simulation in the Active-HDL simulator.

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