Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 12/21/2022
Public

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2.3. Supported Hardware Description Languages

The Intel® Quartus® Prime software provides the following hardware description language (HDL) support for EDA simulators.
Table 3.  HDL Support
Language Support Description

VHDL

  • For VHDL simulation, you compile design files, testbench files, and Platform designer generated RTL files using simulator commands.
  • For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries.
  • Many of the Intel® Quartus® Prime simulation models and IP RTL files are implemented in Verilog or SystemVerilog only. Therefore, you may require a simulator that is capable of VHDL and Verilog HDL mixed language simulation.

Verilog /SystemVerilog

  • For Verilog or SystemVerilog simulation, you compile design files, testbench files, and Platform designer generated RTL files using simulator commands.
  • For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries.
  • There are some IP RTL files that are implemented in VHDL only. Therefore, you may require a simulator that is capable of VHDL and Verilog HDL mixed language simulation.

Mixed HDL

  • If your design is a mix of VHDL, Verilog HDL, and SystemVerilog files, you must use a mixed language simulator.
  • The Questa* Intel® FPGA Edition software supports native, mixed-language (VHDL/Verilog HDL/SystemVerilog) simulation.

    If you have a VHDL-only simulator and need to simulate Verilog HDL modules and IP cores, you can either acquire a mixed-language simulator license from the simulator vendor, or use the Questa* Intel® FPGA Edition simulator.

Schematic

  • You cannot simulate a schematic in any of the simulators that the Intel® Quartus® Prime software supports.
  • To perform RTL simulation of the schematic, you must convert the schematic to HDL format and run RTL simulation on the HDL. The Intel® Quartus® Prime Pro Edition software cannot perform schematic conversion.
  • To perform post-synthesis or post-fit simulation, you must first compile the schematic based design in the Intel® Quartus® Prime software, generate a gate-level Verilog HDL or VHDL simulation netlist, and perform simulation on the gate-level netlist.