2.5.1. Compiling Simulation Model Libraries
For all supported simulators other than Questa* Intel® FPGA Edition, you must compile the appropriate simulation models from the Intel® Quartus® Prime simulation libraries using any of the following methods:
- To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
Note: Once the simulation model compilation starts, the compilation may require from 15 minutes to a full hour, depending on your system. Although the compilation messages may appear paused or incomplete, the compilation is still running correctly.
- Compile Intel® Quartus® Prime simulation models manually with your simulator.
The Intel® Quartus® Prime software includes simulation models for all Intel FPGA IP cores. These models include IP functional simulation models, and device family-specific models in the <installation path>/eda/sim_lib directory. These models include IEEE encrypted Verilog HDL models for both Verilog HDL and VHDL simulation.
Use the compiled simulation model libraries to simulate your design. Refer to your EDA simulator's documentation for information about running simulation.
Intel® Quartus® Prime-Provided Simulation Model Known Restrictions
The following known restrictions apply when using the Intel® Quartus® Prime-provided simulation models:
- The specified timescale precision must be within 1ps when using Intel® Quartus® Prime simulation models.
- X propagation is disabled in the Intel® Quartus® Prime-provided simulation model for the Clock Control Intel® FPGA IP clock divider. Disabling X propagation for the clock divider avoids a lock-up situation in which the clock divider outputs remain at X if an X appears at the clock divider input.
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