Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 4/13/2022
Public
Document Table of Contents

2.2. Supported Simulation Levels

The Intel® Quartus® Prime software provides the following support for RTL and gate-level simulation:
Table 2.  Supported Simulation Levels
Simulation Level Description Simulator Inputs
RTL Cycle-accurate simulation using your Verilog HDL, SystemVerilog, and VHDL design source code with simulation models provided by Intel FPGA and other IP providers.
  • Design source/testbench
  • Intel simulation libraries
  • Intel FPGA IP plain text or IEEE encrypted RTL models
  • IP simulation models
  • Intel FPGA IP functional simulation models
  • Intel FPGA IP bus functional models
  • Verification IP
Gate-level functional Simulation using a post-synthesis or post-fit functional netlist testing the post-synthesis functional netlist, or post-fit functional netlist.
  • Testbench
  • Intel simulation libraries
  • Post-synthesis or post-fit functional netlist
  • Intel FPGA IP bus functional models

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