Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
Public
Document Table of Contents

2.7. Intel FPGA Simulation Basics Revision History

This chapter has the following revision history.

Document Version Intel® Quartus® Prime Version Changes
2022.04.13 22.1
  • Updated simulator versions supported in Simulator Support topic.
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
  • Updated default output directory name to questa in Using the EDA Netlist Writer topic.
2021.10.05 21.3
  • Revised Generating IP Simulation Files steps to include generation of all IP in the design at once.
2021.10.04 21.3
  • Changed chapter title to FPGA Simulation Basics from Simulating Intel FPGA Designs.
  • Added support for Questa* Intel® FPGA Edition simulator throughout.
  • Removed support for ModelSim - Intel FPGA Edition simulator throughout.
  • Updated simulator versions supported in Simulator Support topic.
  • Added precompiled libraries footnote to Supported Hardware Description Languages and Compiling Simulation Model Libraries topics.
  • Revised Running a Simulation (Custom Flow) topic to add missing EDA Netlist Writer step and related links.
  • Replaced "Mentor Graphics" with "Siemens EDA" to reflect current company name.
  • Updated Supported Hardware Description Languages for note on schematic conversion.
  • Revised Scripting IP Simulation to correct typo in step 1.
  • Added links to Incorporating Simulator Setup Scripts from the Generated Template topic.
2021.06.21 21.2
  • Added note about X propagation limit of the Intel® Quartus® Prime-provided clock divider simulation model to the Compiling Simulation Model Libraries topic.
2021.03.29 21.1
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.
2020.10.10 20.1 Renamed --rename to --module_name in The EDA Netlist Writer and Gate-level Netlists
2020.04.30 20.1 Added The EDA Netlist Writer and Gate-level Netlists
2019.04.01 19.1.0
  • Updated supported simulator versions.
2018.12.19 18.1.0
  • Added Simulator Support for Mentor Verification IP Bus Functional Models (BFMs) topic.
2018.09.24 18.1.0
  • Updated supported simulator versions.
2018.05.07 18.0.0
  • Updated list of supported simulation tools to include Cadence Xcelium* Parallel Simulator.
  • Added xcelium_setup.sh to list of simulation setup scripts.
  • Added Sourcing Xcelium* Simulation Setup Scripts topic.

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