3.1. Quick Start Example (ModelSim with Verilog)
- To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
set_user_option -name EDA_TOOL_PATH_MODELSIM <modelsim executable path>set_global_assignment -name EDA_SIMULATION_TOOL "MODELSIM (verilog)"
- Compile simulation model libraries using one of the following methods:
- To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
- Type the following commands to create and map Intel FPGA simulation libraries manually, and then compile the models manually:
vlib <lib1>_ver vmap <lib1>_ver <lib1>_ver vlog -work <lib1> <lib1>
Use the compiled simulation model libraries during simulation of your design. Refer to your EDA simulator's documentation for information about running simulation.
- Compile your design and testbench files:
vlog -work work <design or testbench name>.v
- Load the design:
vsim -L work -L <lib1>_ver -L <lib2>_ver work.<testbench name>
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