4.1. Quick Start Example (VCS with Verilog)
- To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
set_user_option -name EDA_TOOL_PATH_VCS <VCS executable path>set_global_assignment -name EDA_SIMULATION_TOOL "VCS"
- Compile simulation model libraries using one of the following methods:
- To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
Use the compiled simulation model libraries during simulation of your design. Refer to your EDA simulator's documentation for information about running simulation.
- Modify the simlib_comp.vcs file to specify your design and testbench files.
- Type the following to run the VCS simulator:
vcs -R -file simlib_comp.vcs
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