Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 4/13/2022
Public
Document Table of Contents

2.5. Preparing for Simulation

Preparing for RTL or gate-level simulation involves compiling the RTL or gate-level representation of your design and testbench. You must also compile IP simulation models, models from the Intel FPGA simulation libraries, and any other model libraries required for your design.

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