Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
Public
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2.3. Supported Hardware Description Languages

The Intel® Quartus® Prime software provides the following hardware description language (HDL) support for EDA simulators.
Table 3.  HDL Support
Language Support Description

VHDL

  • For VHDL RTL simulation, you compile design files and testbench directly in your simulator. For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design.
  • For gate-level simulation, the Intel® Quartus® Prime EDA Netlist Writer generates a synthesized design netlist VHDL Output File (.vho). You compile the .vho in your simulator.
  • To simulate the model in a VHDL design, you may require a simulator that is capable of VHDL/Verilog HDL co-simulation.

Verilog /SystemVerilog

  • For RTL simulation in Verilog HDL or SystemVerilog, you compile your design files in your simulator. For all supported simulators other than Questa* Intel® FPGA Edition, you must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design.
  • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output File (.vo). Compile the .vo in your simulator.

Mixed HDL

  • If your design is a mix of VHDL, Verilog HDL, and SystemVerilog files, you must use a mixed language simulator. Choose the most convenient supported language for generation of Intel FPGA IP cores in your design.
  • The Questa* Intel® FPGA Edition software supports native, mixed-language (VHDL/Verilog HDL/SystemVerilog) co-simulation of plain text HDL.

    If you have a VHDL-only simulator and need to simulate Verilog HDL modules and IP cores, you can either acquire a mixed-language simulator license from the simulator vendor, or use the Questa* Intel® FPGA Edition simulator.

Schematic

  • To perform RTL simulation of the schematic, you must convert the schematic to HDL format and run RTL simulation on the HDL. The Intel® Quartus® Prime Pro Edition software cannot perform schematic conversion.
  • To perform post-synthesis or post-fit simulation, you must first compile the schematic in the Intel® Quartus® Prime software, generate a gate-level simulation netlist, and perform simulation on the netlist.

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