E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 9/26/2022
Public
Document Table of Contents

4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design

The following provides a general sequential flow for the dynamic reconfiguration transition that takes place within this 100G Ethernet Dynamic Reconfiguration design. When a dynamic reconfiguration transition is triggered through the run_test_dr_sw procedure, it executes the underlying dr_calib_switch procedure with the following sequential flow:

  1. Disable Serdes (through PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide .
  2. Write 0x6 to Ethernet register 0x310 to assert TX and RX soft reset signals.
  3. Perform PMA Analog Reset. For more information, refer to the E-Tile Transceiver PHY User Guide.
  4. To load initial PMA configuration, write 0x01 to transceiver register 0x91 for every transceiver channel.
  5. Perform dynamic reconfiguration transition based on the arguments passed in through the run_test_dr_sw function. The function arguments determines the values of the dynamic reconfiguration registers. With that, the firmware processes the register space modifications accordingly for the Ethernet, Transceiver and RS-FEC configuration register space.
  6. Enable Serdes (through PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  7. Perform dynamic reconfiguration reset (assert and de-assert) through dynamic reconfiguration register 0xE.
  8. Write 0x6 to Ethernet register 0x310 to continue asserting RX soft reset signals.
  9. Enable internal serial loopback.
  10. Trigger PMA adaptation by enabling initial adaptation, check initial adaptation.
  11. Write 0x0 to Ethernet register 0x310 to release TX and RX soft reset signals.

To learn more about the modification performed by the firmware on the Ethernet, Transceiver and RS-FEC registers for various modes, refer to the dynamic_reconfig.cpp file generated in the IP folder.

After you compile the 100G Ethernet E-Tile Dynamic Reconfiguration Design Example and configure it on your device, you can use the procedures to program the IP core.

Table 44.  100G Ethernet Dynamic Reconfiguration Hardware Design Example Functions
Command Setting Description
start_random_pkt_gen_4ch

Starts the packet generator in a random size mode for all four channel lanes.

Example: %start_random_pkt_gen_4ch

stop_pkt_gen_4ch

Immediately stops the packet generator for all four channel lanes.

chkmac_stats $ch

Checks the mac stats counter for the specified channel.

Example:
  • In 100GE mode: %chkmac_stats
  • In 25GE mode: %chkmac_stats 2 for lane 2
run_test_dr

Switches between all available modes and performs the traffic test for each reconfiguration. In 25GE mode, performs four traffic tests, one per each lane.

run_test_dr_sw $elb $mode_curr $mode_target
Switches to a specified mode and performs the traffic test in a loopback mode.
$mode_target options:
  • 100G_rsfec
  • 100G_kpfec 6
  • 100G_rsfec_544 6
  • 100G_nofec
  • 4x25G_rsfec
  • 4x25G_nofec
$more_curr variable supports all target modes.
Note: $mode_curr is not a required parameter.

Example:

In 100GE mode, use this command to switch to 4x25GE:
run_test_dr_sw $elb "100g_rsfec" "4x25G_nofec"

In 25GE mode, use this command to switch to 4x25GE:

run_test_dr_sw 0 "" "4x25G_nofec" as
Note: $mode_curr is not required.
dr_calib_switch $elb $mode_curr $mode_target

Reconfigures to a different mode based on the configuration and a $mode_target variable. Performs the PMA adaptation for the specific mode.

$mode_target options:
  • 100G_rsfec
  • 100G_nofec
  • 100G_kpfec6
  • 100G_rsfec_5446
  • 4x25G_rsfec
  • 4x25G_nofec
$more_curr variable supports all target modes.
Note: $mode_curr is not a required parameter.
Example:
  • In 100GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "100G_rsfec" "4x25G_nofec"
  • In 25GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "" "4x25G_nofec" as $mode_curr isn't required.
dr_reset Resets all signals except the PMA and E-tile Hard IP for Ethernet CSRs.

Below tables describe dr_reset sequence. You need to assert the 4-bit register in a step pattern: 0x8 > 0xC > 0xE > 0xF > 0xE > 0xC > 0x8 > 0x0. Assume 1 ms delay between each step.

Table 45.  Reset sequence assertionThis table illustrates dr_reset[3:0] assertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)

1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
Table 46.  Reset sequence deassertionThis table illustrates dr_reset[3:0] deassertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)

1 1 1 1 1
2 1 1 1 0
3 1 1 0 0
4 0 0 0 0
6
Note: These modes are introduced starting from Intel® Quartus® Prime Pro Edition software version 22.3.

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