E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 9/26/2022
Public
Document Table of Contents

4.4.4. CPRI Design Example Interface Signals

The following signals are hardware dynamic reconfiguration design example signals for the 2.4G/3G/4.9G/6G/9.8G/10G/12G/24G variants.

Table 40.  CPRI Hardware Dynamic Reconfiguration Design Example Interface Signals
Signal Direction Comments
clk100 Input Input clock for reconfiguration. Drive at 100 MHz. The intent is to drive this from a 100 Mhz oscillator on the board.
cpu_resetn Input Global reset for Nios® II system.
i_clk_ref 5 Input 156.25 MHz input clock for channel PLL.
tx_serial_data/_n Output Transmit serial data for channel PLL (PMA direct mode).
rx_serial_data/_n Input Receiver serial data for channel PLL (PMA direct mode).
i_clk_ref_cpri[1:0] Input Input clock for CPRI IP core.

In 24G CPRI IP:

  • [0]: 184.32MHz for high speed mode for 10G/25G Ethernet
  • [1]: 153.6MHz for PMA direct low speed mode for 9.8G CPRI, 6G CPRI, 4.9G CPRI, 3G CPRI, and 2.4G CPRI

In 9.8G CPRI IP:

  • [0]: 153.6 MHz for direct PMA
  • [1]: unused
o_tx_serial Output Transmit serial data
i_rx_serial Input Receiver serial data
5 i_clk_ref is used to provide clock to a PMA direct module, which acts as a channel PLL to supply the required CPRI TX/RX clocks and EMIB clocks.

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