2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
The E-tile Ethernet IP for Intel Agilex FPGA testbench is self-contained and does not require you to drive any input signals.
|clk50||Input||Drive at 50 MHz. The intent is to drive this from a 50 Mhz oscillator on the board.|
|i_clk_ref||Input||Drive at 156.25 MHz.|
|cpu_resetn||Input||Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.|
|i_rx_serial[3:0]||Input||Transceiver PHY input serial data.|
|o_tx_serial[3:0]||Output||Transceiver PHY output serial data.|
|user_led[3:0]||Output||Status signals. Currently the design example drives all of these signals to a constant value of 0. The hardware design example connects these bits to drive LEDs on the target board.|
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