E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 9/26/2022
Document Table of Contents Clocking Scheme

Figure 32. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
Figure 33. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
Note: i_channel_PLL module is E-tile Transceiver PHY specific module that utilizes additional transceiver E-tile channel.

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