Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

ID 683846
Date 9/26/2022

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Document Table of Contents RTL Module Interfaces

For an RTL module to properly interact with other compiler-generated operations, you must support a simplified Avalon® streaming interface at both input and output of an RTL module.

The following diagram shows the complete interface of the myMod RTL module shown in Integration of an RTL Module into an Intel FPGA SDK for OpenCL Pipeline.

In this diagram, myMod interacts with the upstream module through data signals, A and B, and control signals, ivalid (input) and oready (output). The ivalid control signal equals 1 (ivalid = 1) if and only if data signal A and data signal B contain valid data. When the control signal oready equals 1 (oready = 1), it indicates that the myMod RTL module can process the data signals A and B if they are valid (that is, ivalid = 1). When ivalid = 1 and oready = 0, the upstream module is expected to hold the values of ivalid, A, and B in the next clock cycle.

myMod interacts with the downstream module through data signal C and control signals, ovalid (output) and iready (input). The ovalid control signal equals 1 (ovalid = 1) if and only if data signal C contains valid data. The iready control signal equals 1 (ivalid = 1) indicates that the downstream module is able to process data signal C if it is valid. When ovalid = 1 and iready = 0, the myMod RTL module is expected to hold the valid of the ovalid and C signals in the next clock cycle.

myMod module asserts oready for a single clock cycle to indicate it is ready for an active cycle. Cycles during which myMod module is ready for data are called ready cycles. During ready cycles, the module above myMod module can assert ivalid to send data to myMod.

For a detailed explanation of data transfer under backpressure, refer to " Data Transfer with Backpressure " in Avalon Interface Specifications. Ignore the information pertaining to readyLatency option.