Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

ID 683846
Date 9/26/2022

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Document Table of Contents Object Manifest File Syntax of an RTL Module

This section provides the syntax of a simple object manifest file for an RTL module that implements double-precision square root function. The RTL module is implemented in VHDL with a Verilog wrapper.

The following object manifest file is for an RTL module named my_fp_sqrt_double (line 2) that implements an OpenCL™ helper function named my_sqrtfd (line 2).

  1: <RTL_SPEC>
  2:   <FUNCTION name="my_sqrtfd" module="my_fp_sqrt_double">
  3:     <ATTRIBUTES>  
  4:       <IS_STALL_FREE value="yes"/>
  5:       <IS_FIXED_LATENCY value="yes"/>
  6:       <EXPECTED_LATENCY value="31"/>
  7:       <CAPACITY value="1"/>
  8:       <HAS_SIDE_EFFECTS value="no"/>
  9:       <ALLOW_MERGING value="yes"/>
 10:     </ATTRIBUTES> 
 11:     <INTERFACE>
 12:       <AVALON port="clock" type="clock"/>
 13:       <AVALON port="resetn" type="resetn"/>
 14:       <AVALON port="ivalid" type="ivalid"/>
 15:       <AVALON port="iready" type="iready"/>
 16:       <AVALON port="ovalid" type="ovalid"/>
 17:       <AVALON port="oready" type="oready"/>
 18:       <INPUT port="datain" width="64"/>
 19:       <OUTPUT port="dataout" width="64"/>
 20:     </INTERFACE>
 21:     <C_MODEL>
 22:       <FILE name="" />
 23:     </C_MODEL>
 25:       <FILE name="my_fp_sqrt_double_s5.v" />
 26:       <FILE name="fp_sqrt_double_s5.vhd" />
 27:     </REQUIREMENTS>
 28:     <RESOURCES>
 29:       <ALUTS value="2057"/>
 30:       <FFS value="3098"/>
 31:       <RAMS value="15"/>
 32:       <MLABS value="43"/>
 33:       <DSPS value="1.5"/>
 34:     </RESOURCES>
 35:   </FUNCTION>
 36: </RTL_SPEC>
Table 13.  Elements and Attributes in the Object Manifest File
XML Element Description
RTL_SPEC Top-level element in the object manifest file. There can only be one such top-level element in the file. In this example, the name RTL_SPEC is historic and carries no file-specific meaning.

Element that defines the OpenCL function that the RTL module implements. The name attribute within the FUNCTION element specifies the function's name.

You may have multiple FUNCTION elements, each declaring a different function that you can call from the OpenCL kernel. The same RTL module can implement multiple functions by specifying different parameters.

ATTRIBUTES Element containing other XML elements that describe various characteristics (for example, latency) of the RTL module. The example RTL module takes one PARAMETER setting named WIDTH, which has a value of 32. Refer to XML Elements Associated with the ATTRIBUTES Element in the Object Manifest File of an RTL Module for more details other ATTRIBUTES-specific elements.
Note: If you create multiple OpenCL helper functions for different modules, or use the same RTL module with different PARAMETER settings, you must create a separate FUNCTION element for each function.
INTERFACE Element containing other XML elements that describe the RTL module's interface. The example object manifest file shows the Avalon® streaming interface signals that every RTL module must provide (that is, clock, resetn, ivalid, iready, ovalid, and oready).
The resetn signal is active low. Its synchronicity depends on the target device:
Intel® Arria® 10
The resetn signal is asynchronous to the clock signal.
Intel® Stratix® 10
The resetn signal is synchronous to the clock signal. For more information about reset signal timing, see Intel Stratix 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules.
The signal names must match the ones specified in the .xml file. An error occurs during library creation if a signal name is inconsistent.
C_MODEL Element specifying one or more files that implement OpenCL C model for the function. The model is used only during emulation. However, the C_MODEL element and the associated file(s) must be present when you create the library file.
REQUIREMENTS Element specifying one or more RTL resource files (that is, .v, .sv, .vhd, .hex, and .mif). The specified paths to these files are relative to the location of the object manifest file. Each RTL resource file becomes part of the associated Platform Designer component that corresponds to the entire OpenCL system.
Note: The Intel® FPGA SDK for OpenCL™ library feature does not support .qip files. An Intel® FPGA SDK for OpenCL™ Offline Compiler error occurs if you compile an OpenCL kernel while using a library that includes an unsupported resource file type.
RESOURCES Optional element specifying the FPGA resources that the RTL module uses. If you do not specify this element, the FPGA resources that the RTL module uses defaults to zero.