Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 7/31/2023
Public
Document Table of Contents
Give Feedback

2.7.8.1. Viewing Row Clock Region Boundaries

You can use the Chip Planner to visualize the row clock region boundaries, and to ensure that no two PR regions share a row clock region.
  1. Right-click a PR partition name in the Design Partitions Window and click Locate Node > Locate in Chip Planner.
    Figure 30. Row Clock Region Boundaries in Chip PlannerThe green borders in the following floorplan figure indicate clock sectors. A row clock region is one half of a clock sector wide, and one LAB row tall, as indicated by the red box.
  2. In Chip Planner, click the Layers tab and select the Basic layer. The Chip Planner overlays the row clock region boundaries. Adjust the Basic layer settings to display specific items.