Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 7/31/2023
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2.7.9. Planning Clocks and other Global Routing

There are special PR considerations for the planning for clocks and other global routing. For Intel Agilex® 7 and Intel® Stratix® 10 designs, you can use the low skew networks (globals) for clocks or resets.

During the base revision compile, you must route any global signal that any PR persona requires into a destination in the PR region. For clock signals, this destination is a register or other synchronous element and the signal entering the clock input. For a reset, the destination should be fed into the appropriate input.

This requirement occurs because PR only reconfigures the last part of the low skew network. If you do not route the root and middle sections of the network during the base compile, you cannot use that revision for the PR.

Consider an example with a super-set of signals for a PR region that consists of:

  • Three clocks—clk_1, clk_2, and clk_3.
  • Two resets—rst_1 and rst_2.
  • Base PR persona—uses clk_1, clk_2, and rst_1 only.
  • Other personas—use clk_3 and rst_2 only.

In this example, the base persona must have a proper destination for the "unused" clk_3 and rst_2. You can accomplish this by driving a single register with a (*no prune*) directive inside the base PR persona, with clk_3 and reset using rst_2.

Omitting these destinations results in an error during compilation of the PR implementation second persona.