2.7. Partial Reconfiguration Design Considerations
For example, during PR programming, you must ensure that other parts of the system do not read or write to the PR region. You must also freeze the write enable output from the PR region into the static region, to avoid interference with static region operation. If all personas for your design do not have identical top-level interfaces, you must create the wrapper logic to ensure that all the personas appear similar to the static region. Upon partial reconfiguration of a PR region, you must bring the registers in the PR region to a known state by applying a reset sequence. There are specific guidelines for global signals and on-chip memories. The following sections provide design considerations and guidelines to help you create design files for a PR design.
FPGA Device and Software Considerations
- All Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices support partial reconfiguration.
- Use the nominal VCC of 0.9V or 0.95V as per the datasheet, including VID enabled devices.
- To minimize Intel® Arria® 10 and Intel® Cyclone® 10 GX programming files size, ensure that the PR regions are short and wide. For Intel Agilex® 7 and Intel® Stratix® 10 designs, use sector-aligned PR regions.
- The Intel® Quartus® Prime Standard Edition software does not support partial reconfiguration for Intel® Arria® 10 devices, nor provide any support for Intel Agilex® 7 nor Intel® Stratix® 10 devices.
- The current version of the Intel® Quartus® Prime Pro Edition software supports only one Signal Tap File (.stp) per revision.
Design Partition Considerations
- Reconfigurable partitions can only contain core resources, such as LABs, RAMs, and DSPs. All periphery resources, such as the transceivers, external memory interface, HPS, and clocks must be in the static portion of the design.
- To physically partition the device between static and individual PR regions, floorplan each PR region into exclusive, core-only, placement regions, with associated routing regions.
- A reconfiguration partition must contain the super-set of all ports that you use across all PR personas.
Clocking, Reset, and Freeze Signal Considerations
- The maximum number of clocks or other global signals for any Intel® Arria® 10 or Intel® Cyclone® 10 GX PR region is 33. The maximum number of clocks or other global signals for any Intel Agilex® 7 or Intel® Stratix® 10 PR region is 32. In the current version of the Intel® Quartus® Prime Pro Edition software, no two PR regions can share a row-clock.
- PR regions do not require any input freeze logic. However, you must freeze all the outputs of each PR region to a known constant value to avoid unknown data during partial reconfiguration.
- Increase the reset length by 1 cycle to account for register duplication in the Fitter.
- Ensure that all low-skew global signals (clocks and resets) driving into PR regions in base revision compilations have destinations.
- In Intel Agilex® 7 devices, you must use global clock resources to clock M20K RAMs in PR regions. The Fitter issues an error if an M20K in a PR region is driven by a clock port from a locally routed clock.