Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 7/31/2023
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3. Partial Reconfiguration Solutions IP User Guide

The Intel® Quartus® Prime Pro Edition software includes the following Intel® FPGA IP cores that simplify partial reconfiguration implementation.

Instantiate one or more of these IP cores to implement handshake and freeze logic for PR functionality in your design. Alternatively, create your own PR handshake and freeze logic that interfaces with the PR region.

Table 11.  Partial Reconfiguration IP Cores
Intel® FPGA IP Description Usage

Partial Reconfiguration Controller Intel® FPGA IP

Dedicated IP component that sends the partial reconfiguration bitstream for the Intel® Stratix® 10 or Intel Agilex® 7 FPGAs. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA.

One instance per Intel® Stratix® 10 or Intel Agilex® 7 FPGA
Partial Reconfiguration External Configuration Controller Intel® FPGA IP IP component that supports Intel® Stratix® 10 and Intel Agilex® 7 FPGA partial reconfiguration via an external source over dedicated PR pins. One instance per Intel® Stratix® 10 or Intel Agilex® 7 FPGA for external configuration

Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP

Dedicated IP component that sends the partial reconfiguration bitstream to the Intel® Arria® 10 or Intel® Cyclone® 10 GX FPGA. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA.

One instance per Intel® Arria® 10 or Intel® Cyclone® 10 GX FPGA, internal or external configuration.

Partial Reconfiguration Region Controller Intel® FPGA IP

Provides a standard Avalon® memory-mapped interface to the block that controls handshaking with the PR region. Ensures that PR region stops, resets, and restarts, according to the PR handshake.

One instance per PR region.

Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge Intel® FPGA IP

Provides freeze capabilities to the PR region for Avalon® memory-mapped interfaces.

One instance for each interface in each PR region.

Avalon® Streaming Partial Reconfiguration Freeze Bridge Intel® FPGA IP

Provides freeze capabilities to the PR region for Avalon® streaming interfaces.

One instance for each interface in each PR region.