2.4. Internal Host Partial Reconfiguration
With internal host control, an internal controller, a Nios® II processor, or an interface such as PCI Express* ( PCIe* ) or Ethernet, communicates directly with the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block, or with the SDM in Intel® Stratix® 10 and Intel Agilex® 7 devices.
When performing partial reconfiguration with an internal host, use the dedicated PR pins (PR_REQUEST, PR_READY, PR_DONE, and PR_ERROR) as regular I/Os. Implement your static region logic to retrieve the PR programming bitstreams from an external memory, for processing by the internal host.
For example, send the programming bitstreams for partial reconfiguration through the PCI Express* link. Then, you process the bitstreams with your PR control logic and send the bitstreams to the PR IP core for programming. nCONFIG moves the device out of the user mode into the device configuration mode.1