Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

3.5.2. Timing Preservation

The following techniques can help you preserve timing in designs that include the Signal Tap logic analyzer:

  • Avoid adding critical path signals to the .stp file.
  • Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.
  • Specify an fMAX constraint for each clock in the design.