Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/04/2023
Public
Document Table of Contents
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3.4.7. Specifying Pipeline Settings

The Pipeline factor setting indicates the number of pipeline registers that the Intel® Quartus® Prime software can add to boost the fMAX of the Signal Tap logic analyzer.

To specify the pipeline factor from the Signal Tap GUI:

  • In the Signal Configuration pane, specify a pipeline factor ranging from 0 to 5. The default value is 0.
Note: Setting the pipeline factor does not guarantee an increase in fMAX, as the pipeline registers may not be in the critical paths.

Alternatively, you can specify pipeline parameters as part of HDL instantiation, as Creating a Signal Tap Instance by HDL Instantiation describes.

Note: The Signal Tap Intel® FPGA IP is not optimized for the Intel® Hyperflex™ architecture.